Transformer which uses bi-directional synchronous rectification to transform the voltage of an input signal into an output signal having a different voltage and method for effectuating same

ABSTRACT

The present invention provides a transformer which uses bi-directional  syronous rectification to transform the voltage of an input signal from one voltage level to another. The invention provides a transformer which requires less core volume, and hence mass, than conventional transformers, and includes a rectifier for transforming a first time varying input signal, such as a sinusoid or saw tooth signal, into a full-wave rectified voltage signal. A synchronous switch control generates first and second control signals in response to sampling the first time varying voltage signal. A floating drive buffer generates third control signals in response to receiving the second control signals. An AC switching stage transforms the full-wave rectified voltage signal into a first and second series of voltage pulses in response to receiving the first control signals. Each of the first and second series of voltage pulses has a pulse period, T, and a pulse width, ω. The first and second series of voltage pulses have amplitudes generally corresponding to the amplitude of the first time varying voltage signal. In response to receiving the second control signals, a bi-directional synchronous rectifier transforms the first and second series of voltage pulses into a third series of voltage pulses having time varying amplitudes generally corresponding to the amplitude of the first time varying voltage signal, a pulse period T/2, and a pulse width, ω. A low pass smoothing filter transforms the third series of voltage pulses into a second time varying analog voltage signal.

BACKGROUND OF THE INVENTION

The present invention generally relates to the field of transformers,and more particularly, to a transformer which employs bi-directionalsynchronous rectification to transform a signal from one voltage levelto another.

Conventional AC line transformers are used to change AC voltage levelsup or down from an AC line value. Such transformers tend to be large andheavy, requiring a considerable amount of iron or silicon steel in theircores. In many transformer applications, such as found in computers oraircraft, size and/or weight constraints are factors which must beovercome to achieve desired power transform performance. One way toreduce the size of a transformer is to use improved core materialshaving increased magnetic permeability per unit volume. However, acontinuing need exists for even smaller transformers than those alreadyemploying improved magnetic core materials, yet which still providescomparable performance.

Conventional AC line transformers have an output voltage which isdetermined by the turns ratio between its secondary and primarywindings. Since the turns ratio of the windings is fixed, the ratio ofthe output voltage to the input voltage is also fixed. However, thereare some applications in which it may be desirable for a transformer toprovide a variable output voltage. For example, there may beapplications where inputs to various electronic devices may be providedby different power sources and/or at different frequencies, but where aconstant output is required to be provided to a supply load. In otherapplications, it may be necessary to step voltages to different levels,depending on system requirements. Thus, a further need exists for atransformer that can provide a controlled output signal having anadjustable amplitude.

SUMMARY OF THE INVENTION

The present invention provides a transformer which uses bi-directionalsynchronous rectification to transform the voltage of an input signalfrom one voltage level to another. The invention provides a transformerwhich requires less core volume, and hence mass, than conventionaltransformers, and includes a rectifier for transforming a first timevarying input signal, such as a sinusoid or saw tooth signal, into afull-wave rectified voltage signal. A synchronous switch controlgenerates first and second control signals in response to sampling thefirst time varying voltage signal. A floating drive buffer generatesthird control signals in response to receiving the second controlsignals. An AC switching stage transforms the full-wave rectifiedvoltage signal into a first and second series of voltage pulses inresponse to receiving the first control signals. Each of the first andsecond series of voltage pulses has a pulse period, T, and a pulsewidth, ω. The first and second series of voltage pulses have amplitudesgenerally corresponding to the amplitude of the first time varyingvoltage signal. In response to receiving the second control signals, abi-directional synchronous rectifier transforms the first and secondseries of voltage pulses into a third series of voltage pulses havingtime varying amplitudes generally corresponding to the amplitude of thefirst time varying voltage signal, a pulse period T/2, and a pulsewidth, ω. A low pass smoothing filter transforms the third series ofvoltage pulses into a second time varying analog voltage signal.

The AC switching stage preferably generates pulses at a frequency whichmay be up to several orders of magnitude higher (100 or 1000 timesgreater, for example) than the line frequency, typically 60 or 400 Hzand having a duty cycle which may be up to about 98-99% of the pulseperiod. Since the size of a transformer varies roughly linearly andinversely with frequency, a transformer embodying various features ofthe present invention may be manufactured to be much smaller thanconventional transformers having comparable performance characteristics.For example, if the switching frequency is 10 times higher than the linefrequency, the transformer may be 1/10 the size required for aconventional transformer having the same power rating, where size refersto the mass of the transformer core. For 60 Hz systems, the switchingfrequency can easily be set to 6,000 Hz, allowing reduction in thephysical size of the transformer core by a factor of about 100 comparedto the core of a conventional transformer.

Another advantage of the invention is that it may be operated to providea controlled output voltage signal having an adjustable amplitude thatis not completely determined by the turns ratio between the primary andsecondary windings of the transformer.

These and other advantages of the invention will become more readilyapparent upon review of the accompanying specification, including theclaims, and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a transformer embodying various features ofthe present invention.

FIG. 2 is graph representing a sinusoidally varying input signal.

FIG. 3 is a graph representing transformation of the sinusoidallyvarying input signal into a full wave rectified signal.

FIG. 4 is a graph representing transformation of the full wave rectifiedsignal into a first and second series of voltage pulses each having apulse period Γ and a pulse width ω.

FIG. 5 graphically illustrates transformation of the first and secondseries of voltage pulses into a third series of voltage pulses having apulse period Γ/2 and a pulse width ω.

FIG. 6 shows the transformation of the third series of said thirdvoltage pulses into a second sinusoidal voltage signal.

FIG. 7 is a schematic diagram illustrating examples of circuitimplementations of the rectifier, AC switching stage, bi-directionalsynchronous rectifier, and low pass filter of FIG. 1.

FIG. 8 is an example of the synchronous switch control of FIG. 1.

FIG. 9 represents an example of the floating gate buffer of FIG. 1.

FIG. 10 represents a saw tooth waveform.

Throughout the several views, like elements are referenced using likedesignations

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown, a high frequency transformer 10 fortransforming a voltage signal 12 (FIG. 2) from a first voltage level,V₁₂, to a voltage signal 36 (FIG. 6) having a different voltage level,V₃₆. The voltage signal 12 may be a sinusoidal voltage signalcharacterized by V₁ =k₁ sin(2 πft), where V₁ and f represent theamplitude and frequency, respectively, of voltage signal 12, trepresents time, and k₁ is a constant. Signal 12 has alternatingpositive and negative half-cycles 12a and 12b, respectively. Similarly,voltage signal 36 may be characterized by V_(S) =k₂ sin(2 πft), whereV_(S) represents the amplitude of signal 36 and k₂ is a constant, wherek₂ may be less than or greater than k₁, depending on the requirements ofa particular application. Full wave rectifier 14 transforms voltagesignal 12 into a full-wave rectified voltage signal 15 (FIG. 3).Synchronous switch control 23 generates control signals 17 and 19 inresponse to sampling voltage signal 12. A floating drive buffer 21generates control signals 25 in response to receiving the second controlsignals 19. As shown in FIG. 4, AC switching stage 16 transformsfull-wave rectified voltage signal 15 into a voltage signal 18 which isprovided to bidirectional synchronous rectifier 27 in response to ACswitching stage 16 receiving first control signals 17. The voltagesignal 18 comprises a first series 24 of positive and negative voltagepulses 26 and a second series 28 of positive and negative voltage pulses30. The series 24 of voltage pulses 26 and the series 28 of voltagepulses 30 each have a pulse period Γ and a pulse width ω. When inputvoltage signal 12 is a sinusoid, the voltage pulses 26 of the firstseries 24 have amplitudes approximated by V_(S1) =k_(S1) sin(2 πft), andthe voltage pulses 30 of the second series 28 have amplitudesapproximated by V_(S2) =-k_(S1) sin 2 π(ft-ε)!, where V_(S1) and V_(S2)represent the amplitudes of the pulses 26 and 30, respectively, k_(S1)is a constant, and ε represents a phase lag between said first andsecond series of pulses. Preferably, ε≅Γ/2. Bi-directional synchronousrectifier 27 transforms the first series 24 of voltage pulses 26 and thesecond series 28 of voltage pulses 30 into a third series 32 of voltagepulses 34 in response to receiving the third control signals 25generated by the floating drive buffer 21. As shown in FIG. 5, the thirdseries 32 of voltage pulses 34 has a pulse period Γ/2 and a pulse widthω, where the voltage pulses 34 have amplitudes V_(S3) approximated byV_(S3) =k_(S3) sin(2 πft), and k_(S3) is a constant. Low pass filter 35transforms series 32 of voltage pulses 34 into a generally smoothedsinusoidal voltage signal 36. AC switching stage 16 preferably generatespulses at a frequency which may be up to several orders of magnitudehigher (100 to 1000 times greater, for example) than the line frequency,typically 60 or 400 Hz, and having a duty cycle which may be up to about98-99% of the pulse period.

The operation of the transformer 10 is described in more detail withreference to FIG. 7 which illustrates examples of circuitimplementations of the rectifier 14, AC switching stage 16,bidirectional synchronous rectifier 27, and low pass filter 35.Referring to FIG. 7, voltage signal 12 generated by voltage source 60 istransformed into full wave rectified signal 15 by diodes D1 of rectifier14. Signal 15 is provided via signal line 90 to center tap 112 betweenprimary windings 108 and 110 of transformer 104. Transformer 104 alsoincludes a core 115 and center tap 114 between secondary windings 116and 118. The turns ratio of primary windings 108 and 110 to secondarywindings 116 and 118 is 1:N, where N represents a positive rationalnumber. The transformer 104 functionally couples the AC switching stage16 to the bi-directional rectifier 27. Primary windings 108 and 110 maybe considered part of AC switching stage 16 and secondary windings 116and 118 may be considered as part of bi-directional rectifier 27. Thefilter 35 includes inductor 129 and capacitor 131, as shown. In theoperation of transformer 10, four cases with respect to the operation ofthe synchronous rectifier are considered and described with reference toFIG. 7.

In case 1, voltage signal 12 (FIG. 2) and pulses 26 of pulse series 24(FIG. 4) are positive. Referring to FIG. 7, full wave rectified signal15 is provided via conductor line 90 to center tap 112 between primarywindings 108 and 110 of transformer 104. Signal 15 then feeds throughcenter tap 112, primary winding 110, and switch G2. In such case,voltage signal 18 induced in secondary winding 116 feeds through switchA and diode D3 to provide a positive pulse 34 which is filtered by lowpass filter 35 to provide smoothed signal 36 having a positive valueacross output terminals 143 and 145.

In case 2, voltage signal 12 (FIG. 2) is positive while pulses 30 ofpulse series 28 (FIG. 4) are negative. From center tap 112, signal 15 isdirected through primary winding 108, and switch G1. In such case,voltage signal 18, induced in secondary winding 116, feeds throughswitch C and diode D5 to provide a positive pulse 34 which is filteredto provide smoothed signal 36 having a positive value by low pass filter35 across output terminals 143 and 145.

In case 3, voltage signal 12 (FIG. 2) is negative while pulses 26 ofpulse series 26 (FIG. 4) are positive. Signal 15 feeds through centertap 112, primary winding 108, and switch G1. Voltage signal 18 then isinduced in secondary winding 118 and feeds through switch B and diode D4to provide a negative pulse 34 which is filtered by low pass filter 35to provide smoothed signal 36 having a negative value.

In case 4, voltage signal 12 (FIG. 2) and pulses 30 of pulse series 28(FIG. 4) are negative. Full wave rectified signal 15 is provided fromcenter tap 112 to primary winding 110, and switch G2. In such case,voltage signal 18 induced in secondary winding 118 feeds through switchD, and diode D6 to provide a negative pulse 34 which is filtered by lowpass filter 35 to provide smoothed signal 36 having a negative value.

Synchronous switch control 23 shown in FIG. 1 controls the timing ofswitches G1, G2, A, B, C, and D and is described with reference to FIG.8. By way of example, switches G1, G2, A, B, C, and D may be implementedas MOSFETs, which are either ON, represented by a logic value of "1," orOFF, represented by a logic "0." However, the switches A, B, C, and Dmay also, for example, be implemented as bipolar transistors. In suchcase, the diodes D3-D6 shown in FIG. 7 would not be required. A truthtable illustrating The operational logic of switches G1, G2, A, B, C,and D is described below with reference to TABLE 1 and TABLE 2, below.Synchronous switch control 23 includes a comparator 140 for detectingthe polarity of signal 12, a flip-flop 142, AND gates 144, 146, 148,150, 152, and 154, inverter 156, and delay 158, comprised by way ofexample, of NAND gates 160 and 162 connected in series as shown. Theoutput of comparator 140, V_(OUT) is a logic high ("1") when thepolarity of voltage signal 12, V₁₂, is positive, and is a logic low("0") when the V₁₂ is negative, as summarized in TABLE 2. V_(OUT) isprovided to AND gates 148, 150, and inverter 156. Clock signal CLK isprovided to flip-flop 142 having Q and Q outputs. The Q and Q outputsare provided to AND gates 144 and 146, respectively. Clock signal CLK isalso directed through delay 158 to the other inputs of the AND gates 144and 146 so that the flip-flop 142, delay 158 and AND gates 144 togetherprovide a pulse drive system for alternately generating logic HIGH ("1")and LO ("0") signals 17 which are provided to switches G1 and G2,respectively, in a push-pull, i.e., staggered manner.

The output of AND gate 144 is further provided as an input to AND gates148 and 154. AND gates 148 and 150 receive V_(OUT) from comparator 140.Inverter 156 and AND gates 148 and 150 receive V_(OUT) from comparator140. The output of AND gate 146 is further directed to AND gates 150 and152. Inverter 156 inverts V_(OUT) to provide signal V_(OUT-INV), to ANDgates 152 and 154. Thus, it may be appreciated that synchronous switchcontrol 23 operates so that normally open switches A, B, C, and D arebriefly closed and then opened one at a time in a repeating sequencewhich is timed to the push-pull (staggered) switching of switches G1 andG2 in accordance with the logic presented in TABLE 1. The outputs of ANDgates 148, 150, 152, and 154 are provided as signals 19c, 19a, 19d, and19b respectively, which collectively comprise signal 19.

                  TABLE 1                                                         ______________________________________                                        Case No. V.sub.OUT                                                                              G1    G2    A   B     C   D                                 ______________________________________                                        1        1        0     1     1   0     0   0                                 2        1        1     0     0   0     1   0                                 3        0        1     0     0   1     0   0                                 4        0        0     1     0   0     0   1                                 ______________________________________                                    

Preferably, pulses 26 of pulse series 24, and pulses 30 of pulse series28 have a pulse width, ω, and a pulse period T. Pulses 34 of pulseseries 32 have a pulse width ω, but generally have a pulse periodgenerally of about

                  TABLE 2                                                         ______________________________________                                                V.sub.12                                                                             V.sub.OUT                                                      ______________________________________                                                Positive                                                                             1                                                                      Negative                                                                             0                                                              ______________________________________                                    

An example of floating drive 21 is shown by way of example in FIG. 9 toinclude integrated circuit chips 3724 and 3725 coupled by transformer96. The purpose of the floating drive is to assure that the gate voltageof transistor switches A, B, C, and D are established at a predeterminedlevel above the source voltage, which may vary. In FIG. 9, floating gate21 is shown, by way of example, to functionally couple signal 19a toswitch A. However, it is to be understood that a floating gate 21 isused to couple each of signals 19b, 19c, and 19d to switches B, C, andD, respectively.

Suitable control of the frequency and/or pulse width of CLK signal (FIG.8) may be employed to modulate the voltage level of the output signal 36provided by low-pass filter 35 to a desired level. The voltage level ofsignal 36 may such that the ratio V₃₆ /V₁₂ is not necessarily equal tothe ratio N:1, representing the turns ratio between the secondarywindings 116 and 118, and primary windings 108 and 112, where V₃₆ andV₁₂ represent the voltage levels of output signal 36 and input signal12, respectively.

Obviously, many modifications and variations of the present inventionare possible in light of the above teachings. For example, while theinvention for purposes of illustration has been described with referenceto sinusoidal input voltage signals, it is to be understood that thescope of the invention includes its use in conjunction with other timevarying voltage signals input signals which may have, for example, sawtooth and other time varying waveforms, such as saw tooth signal 180,shown in FIG. 10. Therefore, it is to be understood that within thescope of the appended claims, the invention may be practiced otherwisethan as specifically described.

We claim:
 1. A method for transforming a voltage signal from a first voltage level to a second voltage level, comprising the steps of:a) transforming a first time varying voltage signal into a full-wave rectified voltage signal; b) transforming said full-wave rectified voltage signal into a first series of voltage pulses having amplitudes bounded by a first time varying function comprising alternating first positive and first negative half-cycles, and into a second series of voltage pulses having amplitudes bounded by a second time varying function comprising alternating second positive and second negative half-cycles, where said second time varying function is approximately 180 degrees out of phase with respect to said first time varying function; c) transforming said first and second series of voltage pulses into a third series of voltage pulses having amplitudes bounded by a third time varying function comprising alternating third positive and third negative half-cycles, where said third positive half-cycle includes positive voltage pulses and said negative half-cycle includes negative voltage pulses; and d) transforming said third series of said third voltage pulses into a second time varying voltage signal having an amplitude generally defined by said third time varying function.
 2. The method of claim 1 wherein said first and second time varying voltage signals each are periodic time varying voltage signals.
 3. The method of claim 1 wherein said first time varying voltage signal is a sinusoid.
 4. The method of claim 3 wherein said second time varying signal is a sinusoid.
 5. The method of claim 1 wherein said first time varying voltage signal has a saw tooth waveform.
 6. The method of claim 5 wherein said second time varying voltage signal has a saw tooth waveform.
 7. A method for transforming a voltage signal from a first voltage level to a second voltage level, comprising the steps of:a) transforming a first sinusoidal voltage signal into a full-wave rectified voltage signal, where said first sinusoidal voltage signal is characterized by V₁ =k₁ sin(2 πft), V₁ and f represent the amplitude and frequency of said first voltage signal, respectively, t represents time, and k₁ is a constant; b) transforming said full-wave rectified voltage signal into a first and second series of voltage pulses each having a pulse period Γ and a pulse width ω, said voltage pulses of said first series having amplitudes approximated by V_(S1) =k_(S1) sin(2 πft), and said voltage pulses of said second series having amplitudes approximated by V_(S2) =-k_(S1) sin 2 π(ft-ε)!, where V_(S1) and V_(S2) represent the amplitudes of said pulses of said first and second series, respectively, ε represents a phase lag between said first and second series of pulses, and k_(S1) is a constant; c) transforming said first and second series of voltage pulses into a third series of voltage pulses having a pulse period Γ/2 and a pulse width ω, where said voltage pulses of said third series of voltage pulses have amplitudes V_(S3) approximated by V_(S3) =k_(S3) sin(2 πft), and k_(S3) is a constant, and where said third series of voltage pulses comprise alternating positive and negative half-cycles, where said positive half-cycle includes positive voltage pulses and said negative half-cycle includes negative voltage pulses; and d) transforming said third series of said third voltage pulses into a second sinusoidal voltage signal having an amplitude V₂, where V_(S) =k₂ sin(2 πft), and k₂ is a constant.
 8. The method of claim 7 wherein step (b), ε≅Γ/2.
 9. A transformer for transforming a voltage signal from a first voltage level to a second voltage level, comprising:a rectifier for transforming a first time varying voltage signal into a full-wave rectified voltage signal; a synchronous switch control for generating first and second control signals in response to sampling said first voltage signal; a floating drive buffer which generates third control signals in response to receiving said second control signals; an AC switching stage where in response to receiving said first control signals, transforms said full-wave rectified voltage signal into a first series of voltage pulses having amplitudes defined by a first time varying function and a second series of voltage pulses having amplitudes defined by a second time varying function, where said second time varying function is approximately 180 degrees out of phase with respect to said first time varying function; a bi-directional synchronous rectifier for transforming said first and second series of voltage pulses into a third series of voltage pulses in response to receiving said third control signals, where said third series of voltage pulses has amplitudes defined by a third time varying function having alternate positive and negative half-cycles, where said positive half-cycles include positive voltage pulses and said negative half-cycles include negative voltage pulses; and a filter for transforming said third series of said third voltage pulses into a second time varying voltage signal.
 10. The transformer of claim 9 wherein said first time varying voltage signal is a sinusoid having an amplitude V₁ characterized by V₁ =k₁ sin(2 πft), where f represents the frequency of said first time varying voltage signal, t represents time, and k₁ is a constant.
 11. The transformer of claim 10 wherein each of said first and second series of voltage pulses have a pulse period Γ and a pulse width ω, said voltage pulses of said first series having amplitudes V_(S1) approximated by V_(S1) =k_(S1) sin(2 πft), and said voltage pulses of said second series having amplitudes approximated by V_(S2) =-k_(S1) sin 2 π(ft-ε)!, where V_(S1) and V_(S2) represent the amplitudes of said pulses of said first and second series, respectively, ε represents a phase lag between said first and second series of pulses, and k_(S1) is a constant.
 12. The transformer of claim 10 wherein said third series of voltage pulses have a pulse period Γ/2 and a pulse width ω, and said voltage pulses of said third series of voltage pulses have amplitudes V_(S3) approximated by V_(S3) =k_(S3) sin(2 πft), and k_(S3) is a constant.
 13. The transformer of claim 10 wherein second time varying voltage signal has an amplitude V₂, where V_(S) =k₂ sin(2 πft), and k₂ is a constant.
 14. The transformer of claim 11 wherein ε=Γ/2.
 15. The transformer of claim 9 further including:a center tap transformer for coupling said AC switching stage to said bi-directional synchronous rectifier, said center tap transformer having first and second primary windings, and first and second secondary windings; where said AC switching stage includes a first switch for conducting said rectified voltage signal through said first primary winding, and a second switch for conducting said rectified voltage signal through said second primary winding; and said synchronous switch control alternately switches said first and second switches.
 16. The transformer of claim 15 wherein said first and second switches are solid state devices.
 17. The transformer of claim 16 wherein said solid state devices are transistors.
 18. The transformer of claim 15 wherein said bi-directional synchronous rectifier includes third and fourth switches for establishing electrical conductivity through said first secondary winding, and fifth and sixth switches for establishing electrical conductivity with said second secondary winding.
 19. The transformer of claim 18 wherein said synchronous switch control generates control signals for periodically switching one of said third, fourth, fifth, and sixth switches at a time.
 20. The transformer of claim 15 wherein said synchronous switch control includes:a comparator for generating a logic signal, V_(OUT), having a first logic level when said first time varying voltage signal has a first polarity and a second logic level when said first time varying voltage signal has a second polarity, and where said synchronous switch control:a) enables said third switch when V_(OUT) has a first logic level and said second switch is enabled; b) enables said fifth switch when V_(OUT) has said first logic level and said first switch is enabled; c) enables said fourth switch when V_(OUT) has a second logic level and said first switch is enabled; and d) enables said sixth switch when V_(OUT) has said second logic level and said second switch is enabled.
 21. The transformer of claim 15 wherein said AC switching stage receives clock pulses at a pulse frequency which is modulated.
 22. The transformer of claim 15 wherein said AC switching stage receives clock pulses having a duty cycle which is modulated. 